Silicon on insulator (SOI) substrates have been widely employed for devices so as to reduce parasitic capacitance, thereby achieving higher speed performance and improved power consumption.
In these years, there has been an increasing demand for a thin SOI wafer with an SOI layer (silicon layer) of 100 nm or thinner so as to fabricate a fully-depleted SOI device. This is because thinning an SOI layer expectedly leads to higher-speed performance of a device.
Along with the thinning of SOI layers, the in-plane thickness uniformity is demanded more strictly.
Generally, a thin film-SOI wafer is manufactured by the SOITEC process or the SiGen process. In such a process, hydrogen ions are implanted into a donor wafer in advance, the donor wafer is subsequently bonded onto a handle wafer, and a film is transferred from the donor side to the handle side along the hydrogen ion-implanted interface. In this event, however, approximately around 0.1 μm of an ion-implanted defect layer (amorphous layer) is left in the silicon thin film thus transferred, and an RMS surface roughness of approximately several nanometers or higher is introduced onto the surface of the thin film (see, for example, B. Asper “Basic Mechanisms involved in the Smart-Cut(R) process,” Microelectronics Engineering, 36, p233 (1997)).
In this respect, the SOITEC process is carried out as follows. Specifically, both donor and handle wafers are bonded together at room temperature. Then, the wafers are heated to around 500° C. to form air holes, called microcavities, in the hydrogen-implanted interface, thereby causing thermal peeling. Thus, a film is transferred.
Meanwhile, the SiGen process is carried out as follows. Specifically, as a pretreatment of bonding both donor and handle wafers, the donor and handle wafers are subjected to a plasma-surface activation treatment, and the two are bonded (laminated) at room temperature. At this point, they achieve a strong bonding strength. A low-temperature (around 300° C.) heat treatment is performed if necessary. Then, a mechanical impact is applied to a hydrogen ion-implanted interface for peeling, so that a film is transferred. Since the SiGen process can be a low temperature process compared to the SOITEC process, the SiGen process is a method suitable for manufacturing a laminate (for example, silicon on quartz: SOQ) by bonding wafers having different thermal expansion coefficients.
Here, as described above, in the SOITEC process and the SiGen process, an ion-implanted defect layer which is introduced by the ion implantation exists on a surface portion of the peeled surface. Several methods for removing such a defect layer and smoothing the surface have been proposed.
One method is to polish a surface portion by approximately 0.1 μm that is approximately the same thickness as the thickness of an ion-implanted defect layer, thereby removing the ion-implanted defect layer. However, this method has a problem that in-plane uniformity in the thickness of the remaining film is hard to achieve due to unevenness in polishing.
As the other method, a method is conceived in which the crystallinity of a damaged layer is recovered by a high temperature heat treatment, then the surface is subjected to polishing by several tens of nm, called “touch polishing”, to eliminate the asperity of the surface. It is also reported that the surface can be smoothed, in this event, using hydrogen or the like as an atmosphere gas without being subjected to the touch polishing step (see, for example, Nobuhiko Sato and Takao Yonehara “Hydrogen annealed silicon-on-insulator,” Appl Phys Lett Vol 65, pp. 1924 (1994)).
However, as including the high temperature hydrogen heat treatment step, the above different method involves new problems such as metal contamination, warpage of the resulting substrate, increase in the manufacturing cost, reduction in the throughput, and so forth. Furthermore, this method has a disadvantage that uniformity in thickness between substrates, or uniformity in in-plane thickness of a substrate is hard to achieve, because the hydrogen gas etches silicon.
Moreover, if the handle wafer is an SOI wafer made of a low melting point material (such as quartz and glass) other than silicon, the handle wafer can not be subjected to such an additional high temperature heat treatment. Thus, the problem thereof is further serious.
Meanwhile, it is reported that according to observation by an AFM, a surface roughness of approximately 8 nm in RMS and asperity of approximately 64.5 nm in Peak to Valley (P-V) generally exist in a 1×1-μm area of a surface of an SOI wafer manufactured by a hydrogen ion-implantation method (the SOITEC process, the SiGen process, or the like), wherein the surface observed by an AFM is one immediately after transfer of the film (see, for example, “Science of SOI” Chapter 2, Realize Science & Engineering Center Co., Ltd.). Considering that the asperity of 64.5 mm exists even in such a small area of 1×1 μm, presumably a greater asperity (100 nm or more) would exist in the entire surface of the wafer. For this reason, the in-plane roughness of the surface needs to be reduced.